Today's semiconductor industry's technology evolution demands that each organization deliver the IP/ASIC/SOC much ahead of competition to survive in the market place. There is an exponential growth in design complexities in the IP/ASIC/SOC products which challenges every aspect of functional verification, to achieve complete verification of design specification, to build the complete verification eco-system to enable faster verification, to meet functional and code coverage goals, and to meet power and performance criteria.

IC Bridge works closely with customers to address these verification challenges across many industry verticals by providing a combination of service offerings to be the leader in changing technology landscape with innovative and flexible engagement models.

Complete functional verification from Specification to Silicon

IC Bridge team can get involved at any stage of product development to provide a structured and strategic approach to handle and execute verification in an efficient and cost effective way. Services include:

  • Define verification strategy, planning and management to ensure first time right silicon
  • Perform Block / Unit / Full-chip /System level verification
  • Develop efficient modular, reusable and scalable verification environment and components for all levels of verification
  • Develop comprehensive test plans and test scenarios for module level and chip level verification
  • Develop module and chip level coverage plan for achieving maximum functional coverage
  • Perform Constrained Random Testing for ensuring zero bugs
  • Integrate of industry standard Verification IPs for maximum productivity gain
  • Development of module and chip level functional, timing and signal level assertions
  • Verification environment enhancement, migration & customization
  • Develop efficient regression environment and automation scripts to reduce verification cycle

Coverage driven verification

Functional coverage and code coverage are the key indicators of the completeness of the verification. IC bridge team helps in increasing the probability of bug detection by analyzing the 'quality' of stimulus. IC bridge team has a deep understanding of coverage development and analysis techniques to accomplish 100% coverage goals.

Functional Coverage
  • Develop efficient coverage metrics to represent the behavior of the design specification
  • Develop covergroups/coverpoints/coverbins
  • Connect Coverage items with Verification Planner/Manager
  • Perform Coverage analysis and improving coverage by adding test cases
  • Constrain the direction of test vectors to increase the coverage of the design
Code Coverage

Analyze and improve code coverage

  • Statement coverage /line coverage
  • Block/segment
  • Conditional coverage
  • Branch/Path coverage
  • Toggle coverage
  • FSM coverage

Assertion based Verification

Assertions are very critical in verifying functionality against design specification and event sequences. Assertion based verification (ABV) helps reduce the development cycle and improves the quality of the design. Our team members are experts in assertion techniques to ensure consistency between the designer's intention and the actual implementation.

  • Identifying and documenting design specification with assertion
  • Developing immediate and concurrent assertions
  • Developing Invariant, Sequential and Eventual libraries
  • Developing SystemVerilog Assertions (SVA)
  • Developing
    • Functional assertion
    • Timing assertion
    • Signal level assertion
  • Analyze and debug assertion failures
  • Perform assertion coverage

Timing driven verification

Perform Timing verification so that design meets timing specification

Performance driven verification

  • System-level design (Performance analysis tools)
  • Hot-spot analyzer
  • High-level cycle count estimation
  • High-level power analysis
  • High-level chip area estimation
  • On-chip-bus traffic estimation
  • Bandwidth
  • Latency
  • Speed

Power driven verification

  • Perform low power feature verification
  • Verify the design abides the power specifications

Constrained random verification

  • Constrain the direction of the stimulus to increase the coverage of the design.
  • Perform Coverage analysis and improving coverage by constrained test cases

Formal verification

  • Check properties of model with all possible conditions
  • Equivalence checker compares the golden model with the refined model
  • Functional representations are extracted from the designs and compared mathematically

Gate level verification

Gate Level Simulation uses selected functional tests with zero/unit delay (timing checks and specify blocks turned off) simulations to confirm that the netlist is properly hooked up. IC Bridge team is good at performing gate level simulation tasks.

  • Verify that reset release, initialization sequence and boot-up is proper
  • Verify that design changes, incorrect false paths or multi-cycle paths in the constraints
  • Study the activity factor for power estimation
  • Verify that the test structures have been inserted properly
  • Verify that the design has been implemented correctly
  • Check that the static timing constraints have been set up correctly

Hardware-software co-verification

  • Verify with Mixture of SW and HW
  • Verify HW model with Processor Model BFM (Bus functional model)
  • Mixture of pre-verified, unverified components
  • Mixture of different language, different abstraction levels
  • Provide common interface structure between SoC components

Strategic Verification planning and automation

  • Strategic planning
  • Project execution and management
  • Verification Automation

Verification IP & tools Development

  • Develop verification components
  • Develop Checkers, Scoreboard & Monitors

Verification flow methodology and environment set up

  • Set up latest methodology
  • Migrate existing methodology to a new methodology

Our Service Offering

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If you have passion for verification, please email your resume to